Field of the Technology
The disclosure relates to the field of micro-electro-mechanical systems (MEMS), and more particularly to through-wafer interconnects for three dimensional packaging of MEMS devices
Description of the Prior Art
High-aspect ratio through-wafer interconnects technology has a wide spectrum of applications, ranging from multi-layer interconnects in integrated circuits to three dimensional packaging of MEMS sensors. The through-wafer interconnects are typically intended to allow for co-integration of MEMS and integrated circuits by utilizing the front and back side of a wafer. The main challenges for through-wafer interconnect for three dimensional MEMS structures include reduction of via size, low resistance and compatibility with standard semiconductor processing. Via diameter is limited by the electrical contact pad size, which should not exceed 100-200 μm for most MEMS sensors applications. Several approaches have been developed in literature for fabrication of through wafer interconnects, and the strategy for making the via can be divided into two groups. In the first group, through-wafer interconnects are formed by the wafer material, e.g. a doped silicon via. US Patent Pub. 2013/0146994 discloses the method for manufacturing a hermetically sealed structure with silicon through-wafer interconnects. The method for forming vertical via comprises the steps of: patterning and partially etching through the silicon wafer; filling the recesses with an insulator material, like glass or silicon dioxide; removing excess silicon; and depositing a thin metal layer, such as titanium or aluminum, on the silicon parts.
An article entitled “High Density Through Wafer Via Technology”, by T. Bauer, NSTINanotech 2007, Vol. 3, 2007, proposes an idea to isolate a section of a low resistivity silicon wafer laterally by incorporating a trench filled with an isolating material. This isolating trench will most often have the shape of a square or a circle but could also take other shapes if necessary as long as it constitutes a closed loop. The process begins with the formation of the trench using a DRIE process, achieving the necessary high aspect ratio features in up to 600 μm thick substrates. Typical trench width is on the order of 10 to 15 μm. Following the trench etch, the wafer is subject to a high temperature filling of the trenches by a dielectric material. Finally, a chemical-mechanical planarization (CMP) process is applied to the backside of the wafer.
In the second group of prior techniques, a vertical via hole is formed in the wafer using, for example, the Bosch process, followed by an insulating layer and conductive layer deposition. In some cases the conductive layer, like highly doped polysilicon is applied to serve as a via electrical connection itself. In other cases the conductive layer provides a seed for subsequent metal electroplating process. An electroplating process is then used to fill the vertical vias with metal, e.g. copper. In some cases a conductive seed layer is not applied to the via wafer, and then the electroplating process requires using a sacrificial wafer bonded to the through hole via wafer. A sacrificial wafer is usually covered with a thin metal layer to serve for initiating the plating process.
US Pat. Pub. 2010/0052107 teaches the method for fabricating through-wafer interconnects using a molten material with low resistivity drawn into the via holes. The method starts with DRIE etching of via holes in the silicon wafer. After having provided the holes of the desired configuration, the substrate is subjected to a process such that the substrate surface will exhibit a lower wettability than the side walls inside the hole. This can be done by first depositing an oxide layer and then depositing a wetting material. The substrate is then exposed to a molten material having a suitable low resistivity, such as a metal or metal alloys. The difference in wetting capacity of the surface and the side walls in the holes, respectively, will cause the molten metal to be drawn into the holes. The described method is suitable for electronic packaging applications, comprising low resistivity, closely spaced vias. However, this approach is difficult to implement for co-fabrication of vias and silicon on insulator (Sol) sensors on the same wafer. The described approach involves creating through-wafer holes with two openings: one is on the top side of the wafer, another is on the bottom side. Having the second opening is critical to allow gas (air) to exit from the hole, while the molten metal is penetrating inside the hole. In order to adapt the discussed method for the process of co-fabricated SOI sensors with vias, where through holes are not etched, but only blind via holes in the handle substrate are fabricated, significant technology changes are required.
Through-wafer interconnects of the first group mostly have a relatively high resistance as compared to through-wafer interconnects of the second group due to the lower conductivity of silicon as compared to metal. The technology for manufacturing through-wafer interconnects of the second group has a number of limitations. Although through-wafer vias of this kind, reported earlier, have shown satisfactory performance, fabrication of high aspect ratio (better than 10:1) and ultra-low resistance (lower than 200 milli-ohm) interconnects remains problematic.
The four main challenges in the fabrication of metal, e.g. copper electroplated interconnects is uneven filling of the narrow and deep holes due to nonuniform deposition of a seed layer and insufficient wetting of the surface with copper electrolyte, leading to void formation. Besides that, most fabrication processes demonstrated previously are complex, require rather sophisticated fabrication steps, e.g. they either re quire deposition of multiple layers (like insulating layer/seed layer/conductive layer or insulating layer/wetting layer/conductive layer) or bonding a sacrificial wafer. High complexity of the fabrication process in many cases leads to significantly decreased yield.